In conventional circuit emulators and hardware assisted logic simulators, the techniques of timing analysis and clock distribution are carefully applied to ensure correct results. Catastrophic errors occur if the clocking system of the design tool results in setup and hold violations. The objective of improved design debug time is replaced by debugging and tuning the tools rather than the design. In the worst case, all the complexity of designing and fabricating a supercomputer comes into the critical path of verifying a chip.
To ensure accuracy of the model, the hardware accelerator may have to be operated far below its intended capacity and throughput. Worse yet, delay faults in the actual design may be masked by delay faults in the hardware emulator or simulator. Because of the physical hierarchy of a hardware accelerator or emulator (chips, boards, chassis) necessary to contain the amount of logic that can be fabricated onto a single chip, there are many more bottlenecks in the design tools to be addressed.
The present invention builds upon a previously disclosed architecture for hardware acceleration of a simulation of a electronic circuit described in a hardware description language at the register transfer level of abstraction. The description of the circuit is compiled to instructions adapted to be executed on customized evaluation processors which are embodied in application specific integrated circuits or FPGAs.
Thus it can be appreciated that what is needed is a method of compiling a desired design into files suitable for programming a hardware accelerator that increases performance, eliminates vulnerabilities to delay faults, and has scalable capacity.